Conventionally, there has been developed a process for providing a plurality of elements different from each other in terms of a structure on a single chip, and the process is applied to manufacture of a system LSI (Large Scale Integration).
For example, an arrangement in which a CMOS logic circuit and a flash memory such as a nonvolatile memory are provided together on a single chip is conventionally known. Further, Japanese Unexamined Patent Publication No. 196461/2001 (Tokukai 2001-196461)(Publication date: Jul. 19, 2001) discloses such an arrangement that a CMOS (Complementary Metal Oxide Semiconductor) logic circuit and a DRAM (Dynamic Random Access Memory) which is a volatile memory are provided together on a single chip. In this manner, elements different from each other in terms of a structure are provided together on a single chip, so that it is possible to improve an operation speed of the LSI and it is possible to reduce the manufacturing cost thereof.
However, in order to provide elements different from each other in terms of a structure on a single chip, a complicate process is required. Particularly, it is extremely difficult to provide a volatile memory and a nonvolatile memory on a single chip. For example, when a DRAM which is the most general volatile memory and a flash memory which is the most general nonvolatile memory are selected, it is difficult to provide a capacitance constituting the DRAM and a floating gate constituting the flash memory on the same chip. Thus, it is required to develop a technique for providing the volatile memory and the nonvolatile memory together on the same chip.